1. Field of the Invention
The present invention is related to a semiconductor memory device. In particular, the present invention is related to a non-volatile semiconductor memory device capable of storing multi-bit data.
This application claims priority to Korean Patent Application No. 2005-69127, filed Jul. 28, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Semiconductor memory devices are vital components in the design of digital logic systems such as computers, and substantially enable microprocessor-based applications ranging from satellites to consumer electronics. Therefore, advances in the fabrication of semiconductor memory devices, including process enhancements and technological developments achieved through scaling for higher integration density and faster operational speeds, help establish performance standards for other digital logic families. A semiconductor memory device may be a volatile random access memory (RAMs) device or a non-volatile memory device. In RAM, logic information is stored either by setting up the logic state of a bi-stable flip-flop, as in a static random access memory (SRAM), or through charging a capacitor, as in a dynamic random access memory (DRAM). In both SRAMs and DRAMs, the stored data may be read from memory as long as power is supplied to the device, but the stored data is lost when power is not supplied. Hence, SRAMs and DRAMs are called volatile semiconductor memory devices.
Non-volatile semiconductor devices, such as MROMs, PROMs, EPROMs, and EEPROMs, are capable of storing data even when power is not supplied to the device. Depending upon the fabrication technology used, a non-volatile semiconductor device may or may not be reprogrammable (i.e., data storage in the device may be changeable or permanent). Non-volatile semiconductor devices are used for program and microcode storage in a wide variety of applications, such as those common to the computer, avionics, telecommunications, and consumer electronics industries.
A combination of volatile and non-volatile memory storage is available in single chip devices, such as non-volatile SRAM (nvRAM). Such devices are used in systems that require fast, programmable non-volatile memory. In addition, dozens of special memory architectures containing additional logic circuitry adapted to optimize memory device performance for application-specific tasks have been created.
As compared with other types of memory devices, it is relatively difficult to write data to, or erase data from non-volatile semiconductor devices, such as the MROM, PROM, and EPROM. On the other hand, EEPROM devices may be electrically erased or written. As a result, the use of EEPROM devices has been expanded and to auxiliary memories or system programming devices requiring continuous update. In particular, a flash EEPROM (hereinafter referred to as “a flash memory device”) has a higher degree of integration than a conventional EEPROM device, so it is preferable to use a flash memory device in a large auxiliary memory as opposed to a conventional EEPROM device. Also, a NAND-type flash memory device (i.e., a flash memory device comprising NAND-type flash memory) has a higher degree of integration than a well-known, NOR-type flash memory device (i.e., a flash memory device comprising NOR-type flash memory).
A NAND-type flash memory device comprises a memory cell array in which digital information is stored, and the memory cell array comprises a plurality of cell strings (called NAND strings). The flash memory device also comprises a page buffer circuit that stores data in the memory cell array and reads data from the memory cell array. As is well known in the art, memory cells of a NAND-type flash memory device are erased and programmed using Flowler-Nordheim tunneling current. Erase and program methods for NAND-type flash memory devices are disclosed, for example, in U.S. Pat. Nos. 5,473,563 and 5,696,717, the subject matter of which is hereby incorporated by reference in its entirety.
Figure (FIG.) 1 is a block diagram showing a conventional flash memory device. As illustrated in FIG. 1, a flash memory device 10 comprises a memory cell array 12, a row decoder circuit 14, and a page buffer circuit 16. Memory cell array 12 comprises memory cells arranged along rows (i.e., along word lines) and along columns (i.e., along columns that correspond to bit lines). The memory cells are configured in a NAND string structure. The word lines (i.e., the rows) of memory cell array 12 are driven by row decoder circuit 14, and the bit lines (i.e., the columns) are driven by page buffer circuit 16. Each memory cell stores 1-bit data or multi-bit data (e.g., 2-bit data). A page buffer circuit configured to store 2-bit data in each memory cell must be designed differently from a page buffer circuit configured to store 1-bit data in each memory cell. As is well known in the art, 1-bit data is stored in a memory cell by a page buffer circuit comprising one latch, while 2-bit data is stored in a memory cell by a page buffer circuit comprising two latches.
Exemplary page buffer circuits that store 2-bit data in memory cells are disclosed, for example, in U.S. Pat. Nos. 5,768,188; 5,862,974; 5,966,326; and, 5,982,663, the subject matter of which is hereby incorporated by reference in its entirety.
In each of the references mentioned above, the disclosed page buffer circuit comprises two latches and requires sense circuits to transfer data stored in memory cells to respective latches during a read operation. Since sense paths to the respective latches differ, a mismatch between sense margins may arise. In particular, in a flash memory device that stores multi-bit data, read errors are caused by the mismatch of sense margins.
With continuing demand for a higher integration density, flash memory devices are increasingly required to perform various operations, such as cache program, page copy-back, etc. In the cache program operation, while data is programmed during the current program interval, data to be programmed during the next program interval is loaded into a page buffer circuit. In the page copy-back operation, data is moved from one page to another through a page buffer circuit. Like a multi-bit flash memory device, a page buffer circuit requires two latches to perform these operations.
Exemplary page buffer circuits adapted to perform the above-mentioned operations are disclosed, for example, U.S. Pat. Nos. 6,717,857 and 6,671,204, the subject matter of which is hereby incorporated by reference in its entirety.
Unfortunately, a conventional page buffer circuit capable of performing the page copy-back and/or cache program operations has a different structure than a conventional page buffer circuit capable of performing multi-bit programming. Thus, separate page buffer circuits must be provided to perform all of these disparate operations. Unfortunately, the provision of multiple page buffer circuits having different structures drives the cost of memory devices higher.